INFERENCE OPTIMIZATION IN AI SYSTEMS BASED ON TPU AND LPU ARCHITECTURES

Authors

  • Safarov Rustambek Sunnatillo-o’g’li 3rd-Year Student at the Faculty of Physics, Mathematics and Information Technologies, Bukhara State University Author

Keywords:

Domain-specific architecture, Tensor processing unit , Language processing unit, inference, systolic array, deterministic scheduling, energy efficiency, Roofline model.

Abstract

This article investigates the methods for increasing the efficiency of the inference stage in modern artificial intelligence systems, particularly in Large Language Models and deep neural networks. The paper provides a comparative analysis of the hardware and software hierarchy of two distinct Domain-Specific Architectures designed to overcome the limitations of general-purpose graphics processors: Google's Tensor Processing Unit and Groq's Language Processing Unit. The impact of Systolic Arrays and Software-Defined Deterministic Scheduling mechanisms on inference speed, latency, and energy efficiency is substantiated using mathematical models. Simulation and benchmark results indicate that the Language processing unit architecture reduces latency in sequential token generation by up to 8–10 times compared to graphics processors platforms, while the Tensor processing unit delivers higher throughput and energy savings (up to 26.8%) in parallel matrix computations.

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Published

2026-06-09

Issue

Section

Articles

How to Cite

INFERENCE OPTIMIZATION IN AI SYSTEMS BASED ON TPU AND LPU ARCHITECTURES. (2026). EduVision: Journal of Innovations in Pedagogy and Educational Advancements, 2(6), 488-496. https://brightmindpublishing.com/index.php/ev/article/view/2824